meeting date: 25 oct 2005
attending: Arpad Muranyi, Ian Dodd, Todd Westerhoff, Mike LaBonte
           Bob Ross, Ken WIllis, Shang Li
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Review of ARs:

AR: Mike will annotate library modules
AR: Mike fold review comments into macro library
- Converted comments to XML, Writing PERL utility to annotate them into
  VerilogA, VHDL-AMS, and maybe HTML files.

AR: Ken will reconstruct list of interested customers.
- Waiting to create something consumable.
- Same boat as HSPICE with param arrays.

AR: Arpad will resend Cadence DML templates
- done

AR: Arpad write 2-tap driver template
- done

AR: Ken write simple receiver template
- TBD, trying to get Arpad's driver to work

AR: Mike write EQ receiver template
- written, not yet tested

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Bug in IBIS_OUTPUT, etc.
- Arpad sent fixed library last week, more small fixes coming soon

How to simulate in VerilogA without param arrays
- Only Intel simulator works now
- Arpad focusing on making models easy to use
- With param array workaround it works in Spectre
- Shang Li tried, couldn't find a better way than Arpad's implementation
- Arpad asked Ken to test three lines of code currently commented out
  above the line that contains the hard coded array size "3016"

2-tap driver template
- Ken asked Arpad about the commented out section in the template whether
  that is the area that HSPICE cannot do (answer = yes)

eq_amp_rcvr template
- discussed how the termination should be connected plus some other
  circuit details
- need to declare internal nodes too, otherwise looks good
- need to test with a simulator

Mentor simulator is ELDO
- Handles VHDL-AMS and Verilog-AMS.

Web site updates?
- ping Barry

Verilog-A vs. Verilog-AMS
- the problem is that IBIS supports only full AMS languages, and analog
  subsets don't work, becuase the ports are assumed to be pure digital
- what if we added A/D D/A converters to the macro library?
  analog-only (Verilog-A) simulators will not be able to handle it
- need to write a BIRD for IBIS to allow analog-only AMS and define the
  A/D D/A for these the same way as it is done for Berkely SPICE
- ELDO supports only AMS because the ports to the AMS models are digital
- IBIS doesn't support Verilog-A
  - Need to write a BIRD to make analog-only AMS modeling possible
  - IBIS needs a way to distinguish between these analog-only "languages"
    so that the parser could check for the need of the A/D D/A converters
  - What should be the name of these laguages in IBIS?  The official
    Verilog-A is v1.0, or the analog subset of Verilog-AMS v2.x
  - Most tools implement the analog parts of Verilog-AMS v2.x as Verilog-A
  - What about VHDL-A(MS)?  There is really no such official language...
- IBIS should support the analog part of Verilog-AMS, not just Verilog-A
- Arpad suggested to call these Verilog-A(MS) and VHDL-A(MS) in IBIS

A2D conversion differences between simulators
- The receiver logic in Arpad's IBIS buffer model returns a
    1.0 when the pad is above Vinh,
    0.5 when the pad is between Vinl and Vinh,
    0.0 when the pad is betlow Vinl
    HSPICE's B-element returns a
    1.0 when the pad goes above Vinh,
    0.0 when the pad goes below Vinl.
  Should the IBIS bufers in the macro library be compatible with the
  HSPICE B-element, or is it better to have the "X"-state (=0.5V)
  (answer: the "X"-state is needed, keep it)

AR: Ian will draft a BIRD for analog-only AMS support in IBIS

Talk about recruiting next time

Should the VHDL-A(MS) version of the macro model library compatible with
the Verilog-A(MS) version?
- VHDL-A(MS) can do a lot of nice things that Verilog-A(MS) can't, which
  could make the use of the library more convenient for the macro model
  template writers.  It could do better file I/O, opening the IBIS file
  and parse it for all IBIS data needed, including the IV and Vt tables.
- On the other hand, if the two versions of the library are different,
  the template writers would have to make two versions of the templates
  which is highly undesirable
- The concesus was that the VHDL-A(MS) library should be as close as
  possible to the Verilog-A(MS) version even if it is not making use
  of the full potential fo the language

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Next meeting: Tuesday 01 nov 2005.